The 10 Gigabit MAC (per IEEE*  802.3ae) handles frame encapsulation, verification, 10 GbE flow control, and Remote Monitoring/ Simple Network Management Protocol (RMON/ SNMP) statistics management. The IXF18104 MAC also handles the IEEE* 802.3ae Physical Coding Sub-layer (PCS) functions of the 10 Gigabit Ethernet standard. The PCS hardware handles the 64B/66B encoding/decoding to provide the transition density and balance of the 10.3125 Gbps stream.

The system interface supports the industry-standard System Parallel Interface Level 4 Phase 2 (SPI-4.2). This interface is 16 bits wide with 622 Mbps-800 Mbps Double Data Rate (DDR) clocking. The SPI-4.2 interface is Low Voltage Differential Signaling (LVDS). On the line side, the IXF18104 MAC supports the LAN version of the IEEE*  802.3ae XSBI interface. The 16-bit LVDS interface operates at 644 Mbps to support the 10 GbE LAN rate of 10.3125 Gbps.

The IXF18104 MAC also supports an integrated Pseudo Random Bit Sequence (PRBS) packet generator/analyzer for the PCS. Line remote, line local, system remote, and system local loop backs are supported for general development functionality test and debug.

Cortina's IXF1810x family of 10 Gigabit framer devices provide the broadest support for 10 Gbps solutions. The protocols supported are STS-192c POS, 10 Gigabit Ethernet WAN, 10 Gigabit Ethernet LAN, and GFP framing. The table below summarizes the high-level feature set:

Part Number Feature Set IXF18101 STS-192c/STM 64c POS GFP 10 GbE LAN and WAN with MAC, PCS, and WIS SFI-4/XSBI line side interface SPI-4 Phase 2 system-side interface IXF18102 STS-192c/STM 64c POS GFP SFI-4 line side interface SPI-4 Phase 2 system-side interface IXF18103 10 Gigabit Ethernet LAN and WAN PHY with MAC, PCS, and WIS XSBI line side interface SPI-4 Phase 2 system-side Interface IXF18104 10 Gigabit Ethernet LAN PHY with MAC, and PCS XSBI line side interface SPI-4 Phase 2 system-side Interface