The IXF30007 is a fully compliant G.709 digital wrapper device that covers most Optical Transport Network (OTN) applications on a single chip. Built on the technology developed for the IXF30001 (FEC100), the first 10Gbit/s FEC device in the market, the IXF30007 supports enhanced Forward Error Correction (FEC) using concatenated RS-codes that can be set to up to 9dB using various parameters. The IXF30007 is designed for optical transmission applications where the coding gain reached with standard forward error correcting (FEC) algorithms (ITU-T G.975, ITU-T G.709) is not sufficient. The core FEC technology concatenates two Reed-Solomon codes that are configurable in both error correction capability and block length, delivering a coding gain configuration between zero and 30 percent overhead. The IXF30007 consists of two completely separated signal paths referred to as north and south paths. While the north path is primarily designed to operate as a line receiver, the south path may be used as a line transmitter. The IXF30007 forms the basis of a single chip transponder application and, using integrated bridges between both paths, may be configured as a regenerator and provide APS support. The IXF30007 provides all basic functions required for an OTN system, and appropriate configuration of the outer code ensures compliance with the digital signal wrapping technique defined by ITU-T. With integrated overhead processing circuitry and different types of payload mapping, the IXF30007 is a key component in wrapper-based transparent operations, administration, maintenance and provisioning of optical networks. Flexible Design IXF30007 supports both asynchronous and synchronous mapping schemes and has additional features for SONET/SDH data streams such as a Performance Monitor (PM) and post processor. The device I/Os are also compliant with OIF-standards. Synchronous and asynchronous mapping of STM-64 streams is supported for SDH payload data, as proposed by ITU-T G.709. In addition to ITU-T G.709 compliant framing, the IXF30007 may also be combined with any other outer code configuration. Outer and inner RS-Codes are concatenated in the IXF30007 through the use of an interleaver, enabling correction of high input-error-rates as well as burst errors typically found in multiple-wavelength DWDM systems. The integrated, nonintrusive PM in the south path can be used to check incoming payload signal quality by monitoring the B1 and B2 values contained in the regenerator section and line overhead. Monitoring also comprises J0 string extraction and mapping of up to four configurable OH bytes to the processor interface. On the north path, an integrated SOH post processor allows SONET/SDH specific processing. Should severe transmission error occur, such as loss of signal or wrapper frame synchronization, received SONET/SDH data may be replaced by AIS frames. IXF30007 is controlled by a processor interface allowing event-driven communication to reduce processor load. An included IEEE 1149.1 (JTAG) interface may be used to access the internal register bank.