IXF3204/3208
- Quad/Octal T1/E1/J1 Framer
Note - Not recommended for new designs; End-of-Life in process-see PCN
The IXF3208 and IXF3204 are framers for T1/E1/J1 and ISDN primary rate interfaces operating at 1.544Mbps or 2.048Mbps. The IXF3208 is available with 8 ports and the IXF3204 is available with 4 ports. Each framer consists of a receive framer, receive slip buffer, transmit framer, and transmit slip buffer. Each of the framers operates independently, allowing each channel to be individually configured for T1, E1, or J1 operation. To comply with both ANSI T1.403 and ETSI G.821 specifications, comprehensive performance monitoring is done on-chip providing Cortina "On-chip Performance Report Messaging" (PRM). The IXF3208 is the ideal framer for voice and data applications, conforming to V5 and GR-303 specifications with three HDLC controllers per framer. The IXF3208 has an 8-bit microprocessor bus supporting both Intel and Motorola* interfaces. A flexible TDM interface supports bus rates from 1.544MHz to 16.384MHz and industry-standard buses including MVIP, HMVIP, IOM, H100, and CHI. Test and diagnostic functions, such as a full set of loopbacks and Bit Error Rate Testing (BERT) generators/analyzers, are also included. The IXF3208 is available in a 17x17 mm BGA package to enable the design of high-port density, multi-service line cards. To aid in simplifying designs and achieving faster time-to-market, Cortina has developed the IXF3208 Design Assistant and Evaluation Kit. This kit includes a reference design for an 8-port line card that includes the Cortina IXF3208, the protection module, and a comprehensive API and GUI.
Applications
| -- | Integrated Multi-service Access Platforms (IMAPs) |
| -- | Integrated Access Devices (IADs) |
| -- | Voice Gateways |
| -- | Asynchronous Transfer Mode (ATM) Gateways |
| -- | Inverse Multiplexing for ATM (IMA) |
| -- | Wireless Base Stations |
| -- | IP and Packet Routers |
| -- | Frame Relay Access Devices |
Features and Benefits
| Features | Benefits | ||
| -- | Cortina On-chip PRM | -- | Conforms to T1.403 and G.821. Off-loads the system CPU and speeds development by gathering and building the performance monitoring database on-chip, which is an essential part of the network reliability data. |
| -- | T1/E1/J1 Selectability | -- | Enables design of multi-service (T1/E1/J1) platforms. |
| -- | 24 HDLC Controllers | -- | Allows compliance to V5.1, V5.2 and GR-303 specifications. Frame relay applications can be designed without the use of external HDLC controllers. |
| -- | Flexible backplane | -- | Supports non-multiplexed and multiplexed bit and byte replication operations. Offers compatibility with MVIP/ST bus, HMVIP, CHI, and H100 buses. |
| -- | Counters and extensive BERT | -- | Provides convenient performance monitoring, enhanced testing, and flexible loopback functions. |
| -- | API and GUI | -- | Accelerates system development. |
Technical Documents
Product Change Notifications
| PCN103459 - 00 | Telecom & Networking Products, FYI, BGA Tray Standardization | 2006-Sep-02 |
| PCN106766 - 02 | Ethernet Phy, MAC, Framers, T1/E1, Legacy Phy and Framers - Product Marking and Packaging Change, Product Marking | 2006-Oct-12 |
| PCN0107-05.1 | IXF320x Quad T1/E1/J1 Framer, C0, Extended Temp - Product Discontinuance | 2007-Mar-29 |
| DCL200711-01 | Early Shipments due to IT Shutdown and Conversion | 2007-Nov-06 |
| DCL0108-01.0 | Product Code Change | 2008-Jan-04 |
| DCL200802-01.0 | Cortina Systems, Inc. Products (Ethernet Phy, MAC, Framers, T1/E1, Transport and Legacy Phy, & EPON), DCL200802-01.0; FYI – Europe & Middle Eastern Region Orders and Payment Transition | 2008-Feb-05 |
| PCN0308-01.0 | Cortina Systems, Product Marking Change, FYI | 2008-Mar-13 |
| DCL200804-01 | Cortina Systems, Inc. Products (Ethernet Phy, MAC, Framers, T1/E1, Transport and Legacy Phy, & EPON), ; FYI – Latin America Regions Order and Payment Transition, DCL200804-01 | 2008-Apr-14 |