Internal mapping engines provide the required formatting and packet data maintenance into the STS-192c/STM-64c SONET/SDH frame payload. A data-over-Fiber packet mapping mode is supported for test equipment and test functionality verification within a system. The GFP mapping engine can be connected directly to Forward Error Correction (FEC) or OTN digital wrapper devices for GFP, per G.709 specifications.
The system interface is 16 bits wide, features 622Mbps-800Mbps Double Data Rate (DDR) clocking and supports the industry-standard System Parallel Interface Level 4 Phase 2 (SPI-4.2). The SPI-4.2 interface is Low Voltage Differential Signaling (LVDS).
On the line side, the IXF18102 Framer supports the OIF* SerDes Framer Interface Level 4 (SFI-4) interface, which is 16 bits wide with 622 Mbps data rate.
The IXF18102 Framer supports Automatic Protection Switching (APS) for SONET/SDH. Various types of loop backs such as line remote, line local, system remote as well as system local and Synchronous Payload Envelope (SPE) payload test are supported for general development functionality test and debug.
Cortina's IXF1810x family of 10 Gigabit framer devices provide the broadest support for 10 Gbps solutions. The protocols supported are STS-192c POS, 10 Gigabit Ethernet WAN, 10 Gigabit Ethernet LAN, and GFP framing. The table below summarizes the high-level feature set:
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All these devices are pin-, footprint-, and register set-compatible. This allows customers to design one line card for multiple applications, providing cost savings over a single line card with other unsupported features.
The IXF18102 Framer is designed to provide a single chip solution for all STS-192c/STM-64c framing requirements for metro and the core networks.
For customer inquiries, please send to: customerservice@cortina-systems.com and to place orders, send to: orders@cortina-systems.com