IXF18101
- 10Gbps LAN/WAN MAC & OC-192 POS/GFP Framer
The IXF18101 device is a highly integrated solution for STS-192c/STM 64c and 10 Gigabit Ethernet LAN/WAN port applications, as specified in IEEE 802.3ae. The IXF18101 supports various modes of operation for transport of 10 Gigabit Ethernet, High Level Data Link Control (HDLC) frames, Packet over SONET (POS), or Generic Framing Procedure (GFP) packet formatting. Internal mapping engines provide the required formatting and maintenance of packet data into the STS-192c/STM 64c SONET/SDH frame payload. A data-over-fiber packet mapping mode is supported for test equipment and test functionality verification within a system. The 10 Gigabit MAC handles frame encapsulation, verification, 10GbE flow control, and Remote Monitoring/Simple Network Management Protocol (RMON/SNMP) statistics management, per IEEE 802.3ae standards. The IXF18101 also handles the 802.3ae Physical Coding Sub-layer (PCS) and WAN Interface Sub-layer (WIS) functions of the 10 Gigabit Ethernet standard. The PCS hardware handles the 64B/66B encoding/decoding to provide the transition density and balance the 10.3125Gbps stream. The WAN interface sub-layer provides the rate matching mechanism for 9.953Gbps rate transport, as well as the STS-192c/STM 64c framing structure used in WAN PHY applications. The GFP mapping engine can be connected directly to Forward Error Correction (FEC) or Optical Transport Networks (OTN) digital wrapper devices for GFP client mapping directly per G.709. The system interface supports the industry-standard System Packet Interface-level 4 (SPI-4) Phase 2. This interface is 16 bits wide with 622Mbps-800Mbps double data rate clocking. The SPI-4 Phase 2 interface is Low Voltage Differential Signaling (LVDS), which provides the customer with less connection concerns than previous 64-bit High-Speed Transport Layer (HSTL) interfaces. On the line side, the IXF18101 supports both the OIF SFI-4 and IEEE 802.3ae XSBI interfaces. These interfaces can operate at the SONET/SDH 622Mbps rate or the 10 Gigabit Ethernet 622Mbps and 644Mbps rates. An integrated Pseudo Random Bit Sequence (PRBS) packet generator/analyzer for the PCS and WIS blocks (per IEEE 802.3ae clause 49 and 50) is also supported. Loopbacks like line remote, line local, system remote, and system local are supported. The device also supports Synchronous Pay-load Envelope (SPE) payload test loop back for general development functionality test and debug.
Ordering Information
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For customer inquiries, please send to: customerservice@cortina-systems.com and to place orders, send to: orders@cortina-systems.com
| Basename | Order Code | RoHS Status | Media Type | Package | Leads | End of Life |
|---|---|---|---|---|---|---|
| IXF18101 | QCIXF18104EE.B0-998620 | RoHS 6 | TRAY | HL-PBGA | 672 | No |
| IXF18101 | QCIXF18103LEE.B0-998615 | RoHS 6 | TRAY | HL-PBGA | 672 | No |
| IXF18101 | QCIXF18103EE.B0-998625 | RoHS 6 | TRAY | HL-PBGA | 672 | No |
| IXF18101 | QCIXF18102EE.B0-998635 | RoHS 6 | TRAY | HL-PBGA | 672 | No |
| IXF18101 | QCIXF18101EE.B0-998630 | RoHS 6 | TRAY | HL-PBGA | 672 | No |
| IXF18101 | GCIXF18104EE.B0-853149 | RoHS 5 | TRAY | HL-PBGA | 672 | No |
| IXF18101 | GCIXF18103LEE.B0-880096 | RoHS 5 | TRAY | HL-PBGA | 672 | No |
| IXF18101 | GCIXF18103EE.B0-853148 | RoHS 5 | TRAY | HL-PBGA | 672 | No |
| IXF18101 | GCIXF18102EE.B0-853147 | RoHS 5 | TRAY | HL-PBGA | 672 | No |
| IXF18101 | GCIXF18101EE.B0-853146 | RoHS 5 | TRAY | HL-PBGA | 672 | No |