Ever since the IEEE 802.3 Ethernet high-speed study group approved dual project authorization requests at 40 and 100 Gbits/sec that became 802.3ba, most of the debate regarding next-generation Ethernet has centered on issues such as the channel multiplexing for transceiver modules – will it be x4, x10, x12, and when will a copper alternative in a high channel-count module be preserved? Such debates do have implications for FPGA serdes blocks, to be sure, but they may not seem central to development of future Ethernet MACs.

But there’s also the effort by tight coalitions to develop higher-layer protocols. Two of the longer-history efforts are the Interlaken Alliance centered on Cisco Systems and Cortina Systems, and the Scalable System Packet Interface from the Optical Internetworking Forum. These efforts are more interesting for a couple reasons – protocols at data-link layer and above bear more relevance for FPGA glue logic, and the implementation profiles driven by tight groups like Interlaken and OIF may provide more useful near-term guides for 40G and 100G demonstration networks.

This week, Altera Corp. announced that its Stratix IV FPGAs had passed interoperability testing at Interlaken Alliance, using a 6.25-Gbit/sec line rate, and would be able to support a full 10-Gbit line rate. Altera’s instantiation is based on the Interlaken Protocol Rev. 1.2. The test proved interoperability with two Cortina Systems devices, CS1999 and CS3477, as well as PMC-Sierra Inc.’s HyPHY 20G device.

Ultimately, packet transfers based on Interlaken or SPI still must show interoperability with the larger suite of protocols defined for high-speed Ethernet. But conducting such tests now proves the viability of chip-to-chip data transfers that can keep pace with 40G and 100G networks of the future.